A heuristic method to reduce fault candidates for a speedy fault diagnosis

In this paper, we present a heuristic method to reduce fault candidates for an efficient fault diagnosis. This paper uses a matching algorithm for the exact fault diagnosis. But the time consumption of a fault diagnosis using the matching algorithm is huge. So, we present a new method to reduce the fault diagnosis time. The method to reduce the time consumption is separated into two different phases which are a pattern comparison and a back-tracing comparison in failing pattern. The proposed method reduces fault candidates by comparing failing patterns with good patterns during critical path tracing process and comparing back-tracing from non-erroneous POs with back-tracing erroneous POs. The proposed method increases the simulation speed than the conventional algorithms. And this method is also applicable to any other fault diagnosis algorithms. Experimental results on ISCAS´85 and ISCAS´89 benchmark circuits show that fault candidate lists are reduced than those of previous diagnosis methods.