FPGA based asynchronous pipelined multiplier with intelligent delay controller

In this paper, a novel scheme is proposed for the implementation of FPGA based digital systems using asynchronous pipelining technique. To control the asynchronous data flow between stages, an intelligent controller is designed which decides the delay of each stage depending upon the magnitude of the input data (Data Dependent Delay). The intelligent controller has been designed using NIOS II soft core embedded processor in ALTERA EP2C20F484C7 device. But, in this approach, the maximum operating frequency is limited by the excess of logical elements consumed by the microcontroller and the sequential execution of the C code. Hence, the function of NIOS processor to control asynchronous data flow alone has been chosen and is implemented as an equivalent hardware INTASYCON (INTelligent ASYnchronous CONtroller) using hardware description language and the speed of the circuit was evaluated. To verify the efficacy of the proposed approach, 8times8 Braun array multiplier is implemented as external logic to the INTASYCON. The INTASYCON processor calculates the completion time of each stage (based on the logic depth) and accordingly activates the respective dual edge triggered flipflops to transfer data from one stage to next stage. This approach consumes lower power and also avoids the need for global clock signals and their consequences like skew problems.