Multiplier less fast loss less integer DCT for H.264

In the paper we propose a 4 times 4 2-D DCT transpose architecture for use in H.264 video coding standard. Using matrix decomposition the entire 2-D DCT architecture can be made parallel in nature such that the resulting circuit is purely combinational. The DCT values can then be computed in almost the one clock cycle. As the computation clock is independent of the data clock. The actual maximum operating frequency and the throughput of the design can be much higher than the data input rate. The reversible nature of the architecture helps to use the design for IDCT calculation without the change of the design. The FPGA implementation of the proposed design shows that the design throughput of 4.76 Gbps and maximum operating frequency of around 37.24 MHz can be achieved.