DocumentCode
492721
Title
The Javelin: A Java accelerator based on hardware translation method
Author
Lee, Jong-Sung ; Kim, Hyun-Gyu
Author_Institution
Res. & Dev. Center, Adv. Digital Chips Incorporation, Seoul
Volume
01
fYear
2008
fDate
24-25 Nov. 2008
Abstract
In this paper, we propose a Java accelerator named Javelin (Java enhanced language interpreter) based on a hardware translation method. To overcome performance hurdles in translation based accelerators, we assign registers in the host processor for frequently accessed pointers, entries of the stack, local variables, and intermediate values during bytecode execution. We propose an operand exchange unit (OPEXU) for maximizing compatibility and a stack management unit (SMU) with a smart exception handler for minimizing the overhead by stack exceptions. Javelin increases hardware cost less than 9,000 gates including a 256-byte SRAM and does not decrease the clock frequency of host processor. In our experiments, Javelin provides approximately 24.3 times better performance than that of the pure software VM in terms of execution time and it also reduces the memory traffic during Java processing about 81.9%. Consequently, Javelin provides an energy efficient solution for Java processing.
Keywords
Java; program interpreters; virtual machines; Java accelerator; Java enhanced language interpreter; Javelin; hardware translation method; operand exchange unit; stack management unit; Clocks; Costs; Energy efficiency; Frequency; Hardware; Java; Random access memory; Registers; Software performance; Virtual manufacturing; EISC; Hardware Translation; Java Accelerator; Java Virtual Machine;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location
Busan
Print_ISBN
978-1-4244-2598-3
Electronic_ISBN
978-1-4244-2599-0
Type
conf
DOI
10.1109/SOCDC.2008.4815648
Filename
4815648
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