DocumentCode
492723
Title
Segmented scan architecture using segment grouping for test cost reduction
Author
Yang, Myung-Hoon ; Kim, Taejin ; Kim, Yongjoon ; Kang, Sungho
Author_Institution
Dept. Electr.&Electron. Eng., Yonsei Univ., Seoul
Volume
01
fYear
2008
fDate
24-25 Nov. 2008
Abstract
This paper presents a segmented scan architecture to reduce both test application time and test power consumption. The proposed scan architecture partitions scan chains into several segments and groups these segments into several compatible segment groups. All segments within each compatible segment group are filled with test vector data in parallel. Since scan shift operations are limited to segments, the test application time and test power can be significantly reduced.
Keywords
automatic test pattern generation; benchmark testing; integrated circuit testing; segment grouping; segmented scan architechture; test cost reduction; test vector data; Broadcasting; Circuit testing; Clocks; Combinational circuits; Costs; Energy consumption; Instruction sets; Integrated circuit testing; Power engineering and energy; Very large scale integration; design for testability; scan testing; segment grouping; segmented scan; test power; test time;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location
Busan
Print_ISBN
978-1-4244-2598-3
Electronic_ISBN
978-1-4244-2599-0
Type
conf
DOI
10.1109/SOCDC.2008.4815651
Filename
4815651
Link To Document