Title :
Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs
Author :
Kim, Dong-Jun ; Park, Ju-Ho ; Park, Sang-Gyu
Author_Institution :
Div. of Electron. & Comput. Eng., Hanyang Univ., Seoul
Abstract :
Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The performance of the proposed ESD power clamp was successfully verified in a 0.35 um 60 V BCD (bipolar CMOS DMOS) process by TLP (Transmission Line Pulse) measurements.
Keywords :
CMOS integrated circuits; bipolar integrated circuits; electrostatic discharge; field effect transistors; power integrated circuits; transmission lines; Big-FET parasitic capacitance; area-efficient ESD power clamp circuit; bipolar-CMOS-DMOS process; electrostatic discharge; gate-coupled structure; size 0.35 mum; smart power technology; transmission line pulse measurements; voltage 60 V; CMOS process; CMOS technology; Clamps; Distributed parameter circuits; Electrostatic discharge; Parasitic capacitance; Power integrated circuits; Power measurement; Power transmission lines; Pulse measurements; electrostatic discharge (ESD); gate-coupled structure; power clamp circui; smart power technology;
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
DOI :
10.1109/SOCDC.2008.4815664
