Title :
Minimization of the number of PAL macrocells for Moore FSM
Author :
Barkalov, Alexander ; Titarenko, Larysa ; Chmielewski, Slawomir
Author_Institution :
Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Zielona Gora, Poland
Abstract :
The method for decrease of the number of PAL macrocells in the circuit of Moore FSM is proposed. This method is based on the implementation of free outputs of embedded memory blocks to represent the code of the class of pseudo equivalent states. The proposed approach allows minimize the hardware without decreasing digital system performance. An example of application of the proposed method is given.
Keywords :
finite state machines; integrated logic circuits; Moore FSM; PAL macrocells; embedded memory blocks; free outputs; pseudo equivalent states; Digital systems; Hardware; Logic circuits; Logic devices; Macrocell networks; Minimization; Programmable logic arrays; Roentgenium; Switches; System-on-a-chip; Embedded Memory Blocks; Moore Finite-State-Machine; PAL macrocells;
Conference_Titel :
CAD Systems in Microelectronics, 2009. CADSM 2009. 10th International Conference - The Experience of Designing and Application of
Conference_Location :
Lviv-Polyana
Print_ISBN :
978-966-2191-05-9
