Cluster-error correction for through-silicon vias in 3D ICs

The two-dimensional parity check is the optimum single-error-correction code in terms of speed. In this reported work it is employed to develop two sliding schemes for through-silicon-via cluster error correction in three-dimensional ICs. For k bits of source data, the one-dimensional sliding scheme can correct a single cluster error up to about √k bits and more extra discrete errors can be corrected by the two-dimensional sliding scheme. Experiments show that for several hundreds of through-silicon vias (TSVs), two trees of 3-level 2-input exclusive-OR (XOR) gates are almost optimised to encode and decode each interconnect, and the time penalty can be controlled within about 1 ns.