DocumentCode :
494475
Title :
The design of a latency constrained, power optimized NoC for a 4G SoC
Author :
Beraha, Rudy ; Walter, Isask Har ; Cidon, Israel ; Kolodny, Avinoam
Author_Institution :
Qualcomm Corp. Res. & Dev., San Diego, CA
fYear :
2009
fDate :
10-13 May 2009
Firstpage :
86
Lastpage :
86
Abstract :
Network on-Chip (NoC) is being adopted by chip architects as a means to improve design productivity. As the number of modules connected to a bus increase, its physical implementation becomes very complex, and achieving the desired throughput and latency requires time consuming custom modifications. Conversely, NoCs are designed separately from the functional units of the system to handle all foreseen inter-module communication needs. Their inherent scalable architecture facilitates the integration of the system and shortens the time-to-market of complex products. In this work, we discuss and evaluate the design process of a NoC for a state-of-the-art system on-chip (SoC). More specifically, we describe our experience in designing a cost optimized NoC interconnect for a high-performance, power constrained 4G wireless modem. We focus on the power and performance aspects of various module mapping schemes, looking for a tradeoff that is characterized by a minimal power consumption that still meets the timing requirements of all targeted applications. Using a simulated annealing based mapping process, we place the system´s modules on a grid, minimizing the dynamic energy consumed by the transmission of packets over the NoC.
Keywords :
network-on-chip; optimisation; radio access networks; simulated annealing; telecommunication links; telecommunication network routing; NoC interconnect; benchmark; discrete port configurations; end-to-end latency constraints; energy consumption; functional timing requirements; link bandwidths; module mapping schemes; network on-chip; optimization program; packet transmission; pair-wise delays; point-to-point timing requirements; power constrained 4G wireless modem; power consumption; power optimized mapping; simulated annealing-based mapping process; system on-chip; total router area; Constraint optimization; Cost function; Delay; Design optimization; Network-on-a-chip; Process design; Productivity; System-on-a-chip; Throughput; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on
Conference_Location :
La Jolla, CA, USA
Print_ISBN :
978-1-4244-4142-6
Electronic_ISBN :
978-1-4244-4143-3
Type :
conf
DOI :
10.1109/NOCS.2009.5071449
Filename :
5071449
Link To Document :
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