Implementation of a High Performance Multi-axes Motion-Control Chip

The system structure and implementation of a self-developed multi-axes motion-control chip with high performance is proposed. The motion-control chip contains a 32-bit NIOSII Reduced Instruction Set Computing (RISC) processor, a programmable 10/100/1000 Mbps Ethernet Media Access Control (MAC) interface, 4-channel optic encoder interface, 4-channel pulse generator, digital inputs and outputs, flash and static memory interfaces and LCD interface. Discussions are focused on the kernel modules of mentioned chip system including control pulses generator, quadrature encoder interface, and Ethernet MAC. Simulation results and applications are also presented to demonstrate the effectiveness of the proposed motion-control chip which could be widely used for developing high performance stand alone motion controllers and motion control application systems.