• DocumentCode
    49514
  • Title

    Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement

  • Author

    Gwangsun Kim ; Lee, Michael Mihn-Jong ; Kim, John ; Lee, Jae W. ; Abts, Dennis ; Marty, Michael

  • Author_Institution
    Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
  • Volume
    63
  • Issue
    6
  • fYear
    2014
  • fDate
    Jun-14
  • Firstpage
    1487
  • Lastpage
    1500
  • Abstract
    Many-core processors will have many processing cores with a network-on-chip (NoC) that provides access to shared resources such as main memory and on-chip caches. However, locally-fair arbitration in multi-stage NoC can lead to globally unfair access to shared resources and impact system-level performance depending on where each task is physically placed. In this work, we propose an arbitration to provide equality-of-service (EoS) in the network and provide support for location-oblivious task placement. We propose using probabilistic arbitration combined with distance-based weights to achieve EoS and overcome the limitation of round-robin arbiter. However, the complexity of probabilistic arbitration results in high area and long latency which negatively impacts performance. In order to reduce the hardware complexity, we propose an hybrid arbiter that switches between a simple arbiter at low load and a complex arbiter at high load. The hybrid arbiter is enabled by the observation that arbitration only impacts the overall performance and global fairness at a high load. We evaluate our arbitration scheme with synthetic traffic patterns and GPGPU benchmarks. Our results shows that hybrid arbiter that combines round-robin arbiter with probabilistic distance-based arbitration reduces performance variation as task placement is varied and also improves average IPC.
  • Keywords
    asynchronous circuits; cache storage; circuit complexity; graphics processing units; multiprocessing systems; network-on-chip; performance evaluation; probability; EoS; GPGPU benchmarks; distance-based weights; equality-of-service; hybrid arbiter; locally-fair arbitration; location-oblivious task placement; low-overhead network-on-chip support; main memory; many-core processors; multistage NoC; on-chip caches; performance variation reduction; probabilistic arbitration complexity; probabilistic distance-based arbitration; round-robin arbiter limitation; shared resources; synthetic traffic patterns; system-level performance; Bandwidth; Measurement; Probabilistic logic; Program processors; Routing; System-on-a-chip; Network-on-chip (NoC); arbitration; equality-of-service (EoS);
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2012.241
  • Filename
    6319294