Fast Variation-Aware Statistical Dynamic Timing Analysis

A statistical dynamic timing analysis framework is presented to study the impact of catastrophic defects and process variation on the delay behavior of a digital circuit considering the effect of gate switching on delays. It uses object-oriented programming and levelized code generation techniques to achieve fast runtimes with linear time complexity as the number of gates increases. The generated functional delay model along with experiments and statistical modules are compiled to machine code before execution; and random transition vectors approximate the delay profiles useful for virtual speed grading and yield estimation.