DocumentCode :
495443
Title :
SpMT WaveCache: Exploiting Thread-Level Parallelism in WaveScalar
Author :
Pei, Songwen ; Wu, Baifeng ; Du, Min ; Chen, Gang ; Marzulo, Leandro A J ; Franca, Felipe M G
Author_Institution :
Sch. of Comput. Sci., Fudan Univ., Shanghai, China
Volume :
3
fYear :
2009
fDate :
March 31 2009-April 2 2009
Firstpage :
530
Lastpage :
535
Abstract :
Speculative multithreading (SpMT) increases the performance by means of executing multiple threads speculatively to exploit thread-level parallelism. By combining software and hardware approaches, we have improved the capabilities of previous WaveScalar ISA on the basis of transactional memory system for the WaveCache Architecture. Threads are extracted at the course of static compiling, and speculatively executed as a thread-level transaction that is supported by extra hardware components, such as thread-context-table (TCT) and thread-memory-history (TMH). We have evaluated the SpMT WaveCache with 6 real benchmarks from SPEC, Mediabench and Mibench. On the whole, the SpMT WaveCache outperforms superscalar architecture ranging from 2times to 3times, and great performance gains are achieved over original WaveCache and transactional WaveCache as well.
Keywords :
cache storage; memory architecture; multi-threading; Mediabench; Mibench; SPEC; SpMT WaveCache; WaveCache architecture; WaveScalar ISA; speculative multithreading; superscalar architecture; thread-context-table; thread-level parallelism; thread-level transaction; thread-memory-history; transactional WaveCache; transactional memory system; Computer architecture; Computer science; Hardware; Instruction sets; Multithreading; Out of order; Parallel processing; Program processors; Protocols; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Information Engineering, 2009 WRI World Congress on
Conference_Location :
Los Angeles, CA
Print_ISBN :
978-0-7695-3507-4
Type :
conf
DOI :
10.1109/CSIE.2009.35
Filename :
5170898
Link To Document :
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