Design of a Configurable and Extensible Tcore Processor Based on Transport Triggered Architecture

Author

Guo, Wei ; Wei, Jizeng ; Yao, Yongbin ; Shi, Zaifeng ; Wang, Su

Author_Institution

Sch. of Comput. Sci. & Technol., Tianjin Univ., Tianjin, China

Volume

3

fYear

2009

fDate

March 31 2009-April 2 2009

Firstpage

536

Lastpage

540

Abstract

A hardware design of a configurable and extensible processor named Tcore, which is based on transport triggered architecture (TTA), is presented in this paper. Due to its flexibility, the Tcore can be used as an application specific processor, especially as a coprocessor for different DSP applications. We have configured Tcore to an instruction level parallel processor to support the application of MP3 IMDCT in a SoC and have been fully verified on FPGA. The results show the advantage of using this configurable processor in terms of performance in computation, flexibility in application, limited effort in design and reduction on silicon area.

Keywords

coprocessors; discrete cosine transforms; field programmable gate arrays; instruction sets; logic design; logic testing; parallel processing; system-on-chip; DSP; FPGA; MP3 IMDCT; SoC; application specific processor; configurable Tcore processor design; coprocessor; instruction level parallel processor; logic testing; transport triggered architecture; Application software; Application specific processors; Computer architecture; Computer science; Coprocessors; Design engineering; Hardware; Multiprocessor interconnection networks; Radio frequency; Registers; IMDCT; MP3; SoC; Transport Triggered Architecture; configurable and extensible processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Information Engineering, 2009 WRI World Congress on

Conference_Location

Los Angeles, CA

Print_ISBN

978-0-7695-3507-4

Type

conf

DOI

10.1109/CSIE.2009.233

Filename

5170899