• DocumentCode
    496051
  • Title

    An intelligent deflection router for networks-on-chip

  • Author

    Radetzki, Martin ; Kohler, Adán

  • Author_Institution
    Inst. fur Tech. Inf., Univ. Stuttgart, Stuttgart, Germany
  • fYear
    2009
  • fDate
    25-26 June 2009
  • Firstpage
    57
  • Lastpage
    62
  • Abstract
    Future manycore systems-on-chip will employ packet-switched, multi-hop interconnection networks-on-chip (NoC). In order to cope with disturbances from, e.g., faults or local traffic overload, some degree of intelligence and adaptivity has to be built into NoC routers. They need to know about their own and their environment´s fault and traffic status and take this information into account when making routing decisions. In this paper, we present an approach that selects optimized routes based on a routing cost function which includes route length, fault status, and traffic congestion all at the same time. We investigate the effect on communication performance for an implementation of deflection routing as well as the router´s area complexity and compare them against traditional NoC deflection routers.
  • Keywords
    integrated circuit interconnections; network-on-chip; telecommunication network routing; intelligent deflection router; multihop interconnection NoC; networks-on-chip; optimisation route; routing cost function; Circuit faults; Cost function; Fault diagnosis; Fault tolerance; Intelligent networks; Load management; Network-on-a-chip; Routing; Switches; Telecommunication traffic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Intelligent solutions in Embedded Systems, 2009 Seventh Workshop on
  • Conference_Location
    Ancona
  • Print_ISBN
    978-1-4244-4838-8
  • Electronic_ISBN
    978-88-87548-02-0
  • Type

    conf

  • Filename
    5186376