DocumentCode
496120
Title
System-Level Behavior Construction and Design Risk Evaluation Based on United Model for System-on-Chip
Author
Yu, Jinshan ; Li, Tun
Author_Institution
Nat. Lab. of Analog IC´´s, Sichuan Inst. of Solid State Circuits, Chongqing, China
Volume
1
fYear
2009
fDate
25-26 July 2009
Firstpage
382
Lastpage
386
Abstract
A novel environment-driven and model-based system-level design behavior construction and risk assessment method for SoC is proposed. Through the way, we can not only construct system behavior scenarios, identify the critical scenarios and components, but also assess their risk, which can be used to guide the verification policy for SoC.
Keywords
risk management; system-on-chip; design risk evaluation; model-based system-level design behavior construction; risk assessment method; system-on-chip; Communication system control; Computer architecture; Computer science; Protocols; Risk analysis; Risk management; Solid state circuit design; System-level design; System-on-a-chip; Unified modeling language; Behaviors Construction; Model; Risk Evaluation; System-Level;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology and Computer Science, 2009. ITCS 2009. International Conference on
Conference_Location
Kiev
Print_ISBN
978-0-7695-3688-0
Type
conf
DOI
10.1109/ITCS.2009.82
Filename
5190092
Link To Document