Design of Low Power Ternary Magnitude Comparator Based on Multi-valued Switch-Signal Theory

Author

Zeng, Xiaopang ; Wang, Pengjun

Author_Institution

Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China

Volume

1

fYear

2009

fDate

18-19 July 2009

Firstpage

258

Lastpage

261

Abstract

By analyzing the multi-valued switch-signal theory (MVSST), this paper presents a novel design scheme of low power ternary magnitude comparator (TMC). The scheme adopt switch-level design technique, on one hand, full-swing output signal improves noise margins, on the other hand, the reducing number of MOS insuring the simple circuit and small area. At last, the PSPICE simulation results indicate that the novel scheme have correct logic function and the character of clearly low power.

Keywords

MOS digital integrated circuits; comparators (circuits); logic design; low-power electronics; multivalued logic circuits; MOS; PSPICE simulation; circuit design; full-swing output signal; low power ternary magnitude comparator; multivalued logic; multivalued switch-signal theory; switch-level design technique; CMOS technology; Circuits and systems; Delay; Digital circuits; Energy consumption; Multivalued logic; Signal design; Signal processing; Switches; Switching circuits; MVSST; TMC; circuit design; low power; multi-valued logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Processing, 2009. APCIP 2009. Asia-Pacific Conference on

Conference_Location

Shenzhen

Print_ISBN

978-0-7695-3699-6

Type

conf

DOI

10.1109/APCIP.2009.72

Filename

5197045