Author :
Yaegashi, T. ; Okamura, T. ; Sakamoto, W. ; Matsunaga, Y. ; Toba, T. ; Sakuma, K. ; Gomikawa, K. ; Komiya, K. ; Nagashima, H. ; Akahori, H. ; Sekine, K. ; Kai, T. ; Ozawa, Y. ; Sugi, M. ; Watanabe, S. ; Narita, K. ; Umemura, M. ; Kutsukake, H. ; Sakuma, M
Author_Institution :
Center for Semicond. R&D, Toshiba Corp., Yokohama, Japan
Abstract :
20 nm-node planer MONOS NAND Flash memory is developed for the first time. Excellent performances such as fast program speed are realized without using FinFET structure. Furthermore, potential of tight Vth distribution is confirmed using 50 nm-node cells. These properties indicate that planer MONOS cell technology developed in this work can be one of candidates for multi-level NAND Flash memory with 20 nm-node and beyond.
Keywords :
NAND circuits; flash memories; MONOS NAND Flash memory; multilevel NAND Flash memory; planer MONOS cell technology; size 20 nm; size 50 nm; Dielectric films; Electrodes; FinFETs; Laboratories; Large scale integration; MONOS devices; Manufacturing processes; Metalworking machines; Semiconductor device manufacture; Voltage;
