DocumentCode :
497160
Title :
Applications of advanced transmission electron microscopy techniques in gate stack scaling
Author :
Stemmer, Susanne ; LeBeau, James M. ; Cagnon, Joël ; Hwang, Yoontae ; Engel-Herbert, Roman
Author_Institution :
Mater. Dept., Univ. of California, Santa Barbara, CA, USA
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
198
Lastpage :
199
Abstract :
Advanced gate dielectric stacks are comprised of multiple layers of different materials, including high-k gate dielectrics, high-mobility semiconductor channels, metal gate electrodes and interfacial layers with sub-nanometer thickness. The composition, point defect chemistry, interface atomic structure and interaction between the layers determine the properties of novel gate stacks. This paper reviews recent applications of advanced transmission electron microscopy techniques to determine the atomic structure and defects in advanced gate stacks.
Keywords :
CMOS integrated circuits; dielectric materials; transmission electron microscopy; different materials; gate dielectric stacks; gate stack scaling; high-k gate dielectrics; high-mobility semiconductor channels; interface atomic structure; interfacial layers; metal gate electrodes; point defect chemistry; sub-nanometer thickness; transmission electron microscopy; Transmission electron microscopy; CMOS; TEM; advanced channel materials; work function engineering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7
Type :
conf
Filename :
5200597
Link To Document :
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