DocumentCode :
497210
Title :
A novel thin BOX SOI technology using bulk Si wafer for system-on-chip (SoC) application
Author :
Oh, Chang Woo ; Bae, Hyun Jun ; Ha, Jae Kyu ; Park, Sang Jin ; Park, Bok Kyung ; Kim, Dong-Won ; Chung, TaeYoung ; Oh, Kyung Seok ; Lee, Won-Seong
Author_Institution :
Adv. Technol. Dev. Team 1, Samsung Electron. Co., Yongin, South Korea
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
96
Lastpage :
97
Abstract :
In this article, we proposed a novel SOI technology for introducing thin BOX SOI structure into bulk Si wafer and demonstrated thin body SOI transistors with the thinnest BOX thickness of 7 nm ever reported. Owing to thin BOX and thin body structure, they showed good VTH controllability and effective ION/IOFF controllability exceeding thick BOX transistors. Their small variation was also confirmed. For further scaling, triple-gate nanowire transistor was also achieved by modifying the field oxide structure. Thus, a novel thin BOX SOI technology using bulk Si wafer must be very useful in controlling the transistor performance/power consumption, as well as in reducing the manufacturing cost.
Keywords :
MOSFET; low-power electronics; nanoelectronics; nanowires; silicon-on-insulator; system-on-chip; Ion/Ioff controllability; Si-SiO2; bulk silicon wafer; field oxide structure modification; manufacturing cost reduction; power consumption; power control; size 7 nm; system-on-chip; thick BOX transistor; thin BOX SOI MOSFET; thin BOX SOI technology; thin body SOI transistor performance; triple-gate nanowire transistor; Controllability; Fabrication; Germanium silicon alloys; MOSFETs; Manufacturing; Silicon germanium; Silicon on insulator technology; Substrates; System-on-a-chip; Thickness control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7
Type :
conf
Filename :
5200647
Link To Document :
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