Title :
Physical understanding of Vth and Idsat variations in (110) CMOSFETs
Author :
Saitoh, Masumi ; Yasutake, Nobuaki ; Nakabayashi, Yukio ; Uchida, Ken ; Numata, Toshinori
Author_Institution :
Corp. R&D Center, Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
In this paper, the first systematic study of Vth variations (sigmaVth) and Idsat variations (sigmaIdsat) in (110) n/pMOSFETs is presented. sigmaVth in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance sigmaVth in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize sigmaVth in (110) FETs. We also found that sigmaIdsat is determined by both sigmaVth and the degree of velocity saturation. sigmaIdsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.
Keywords :
CMOS integrated circuits; MOSFET circuits; integrated circuit design; CMOSFET; interface traps; ion channeling; n/pFET; n/pMOSFET; optimum channel impurity design; CMOS technology; CMOSFETs; Doping profiles; FETs; Impurities; Laboratories; Large scale integration; MOSFETs; Research and development; Resource description framework;
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7