Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

Author

Suk, Sung Dae ; Li, Ming ; Yeoh, Yun Young ; Yeo, Kyoung Hwan ; Ha, Jae Kyu ; Lim, Hyunseok ; Park, HyunWoo ; Kim, Dong-Won ; Chung, TaeYoung ; Oh, Kyung Seok ; Lee, Won-Seong

Author_Institution

Semicond. R&D Center, Samsung Electron. Co., Yongin, South Korea

fYear

2009

fDate

16-18 June 2009

Firstpage

142

Lastpage

143

Abstract

Sub 5 nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure. Performance of the poly Si channel is compared with that of the single Si channel. On-state current of n-FET has attained to 802 uA/um for single Si channel, while 471 uA/um for poly Si channel, which is 60 % of performance of the single Si channel at L_G ~ 5 nm due to the enhancement of ballistic efficiency. At the extremely small L_G of around 5 nm, we also investigate off-leakage current with boosted BJT operation.

Keywords

MOSFET; elemental semiconductors; silicon; silicon-on-insulator; BJT operation; SOI structure; Si; ballistic enhancement efficiency; n-FET; off-leakage current; on-state current; silicon-on-insulator; size 5 nm; trigate nanowire MOSFET; Amorphous materials; Costs; FETs; Logic devices; MOSFETs; Oxidation; Research and development; Space technology; Stacking; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2009 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-3308-7

Type

conf

Filename

5200665