Post-Fabrication self-convergence scheme for suppressing variability in SRAM cells and logic transistors

A new concept for suppressing variability in SRAM cells and logic transistors is proposed. The novel method utilizes self-convergence mechanisms: V_th of transistors with low V_th is selectively raised by applying high bias voltage to all transistors collectively after chip fabrication, resulting in lower variability in retention-noise-margin (RetNM) in SRAM and V_th in logic transistors. The concept is validated by simulation and experiments.