• DocumentCode
    497235
  • Title

    26 nm gate length CMOSFETs with aggressively reduced silicide position by using carbon cluster co-implanted raised source/drain extension structure

  • Author

    Yako, Koichi ; Yamamoto, Toyoji ; Uejima, Kazuya ; Hase, Takashi ; Hane, Masami

  • Author_Institution
    LSI Fundamental Res. Lab., NEC Electron. Corp., Sagamihara, Japan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    160
  • Lastpage
    161
  • Abstract
    We demonstrated 26 nm gate length CMOSFETs with an aggressively reduced silicide position down to 5 nm from the gate edge realized about one decade of order junction leakage reduction, and 10% Ion improvement for both N and PFET. Carbon cluster co-implanted raised source/drain extension (SDE) structure, that enables to enhance SDE boron concentration at the silicide interface and to reduce deep halo dosage without short channel effect degradation, is a key to achieve both low parasitic resistance and low junction leakage.
  • Keywords
    MOSFET; semiconductor technology; CMOSFET; aggressively reduced silicide position; carbon cluster; gate edge; order junction leakage reduction; silicide interface; size 26 nm; source-drain extension structure; Annealing; Boron; CMOSFETs; Degradation; Implants; Impurities; Large scale integration; MOSFET circuits; National electric code; Silicides;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2009 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-3308-7
  • Type

    conf

  • Filename
    5200672