DocumentCode :
497236
Title :
The fabrication of low leakage junction with ultra shallow profile by the combination annealing of 10-ms low power and 2-ms high power FLA
Author :
Onizawa, Takashi ; Kato, Shinichi ; Aoyama, Takayuki ; Ikeda, Kazuto ; Ohji, Yuzuru
Author_Institution :
Semicond. Leading Edge Technol., Tsukuba, Japan
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
162
Lastpage :
163
Abstract :
We propose the suitable FLA method for pFET device activation by using flexibly-shaped-pulse FLA (FSP-FLA). For the activation annealing by FLA on B without pre-amorphous implantation (PAI) process, increase in preheat temperature before flash is the most effective. By using FSP-FLA, ~1000degC 10-ms preheat was performed. It achieves very shallow and high activated junction without PAI equivalently to that by the conventional FLA with PAI. By using the FSP-FLA without PAI, drastically reductions of the junction leakage (JL) both of p- and nFET were achieved.
Keywords :
CMOS integrated circuits; MOSFET; incoherent light annealing; activation annealing; annealing; flash lamp annealing; flexibly-shaped-pulse FLA; high power FLA; junction leakage; low leakage junction fabrication; low power FLA; nFET; pFET device activation; time 10 ms; time 2 ms; ultra shallow-junction; Annealing; CMOS process; Degradation; Electronic mail; Fabrication; Ion implantation; Lead compounds; Optical pulse shaping; Shape; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7
Type :
conf
Filename :
5200673
Link To Document :
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