Decomposition algorithm for power delay product optimization in Wallace multiplier

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products or even in line operated devices in order to avoid larger heat sinks. Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. The general objective of our work is to investigate the area and power-delay performances of 8 bit and 16 bit multiplier combining both Wallace tree and decomposition algorithm. This decomposition logic improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. We have analyzed area and power-delay performances using different type of adder structures using different logic families CMOS, HYBRID AND CPL. With the help of these designs, it would be possible to design highly power efficient processor with less area, especially digital signal processors.