High performance architectures for recursive loop algorithms

The goal of any digital design is to maximize the performance while keeping the cost down. In digital communication systems, high speed transmission requires implementation of high speed digital circuits which include adaptive equalizers, encoders and other signal processing algorithms. The recursive loops present in these algorithms limit the speed of operation, since these loops contain nonlinear operations (such as the quantization operation). Examples of these algorithms are differential pulse code modulation (DPCM), Decision feedback equalizers (DFE´s). The internal feedback in these loops makes it difficult to implement recursive loops concurrently using either pipelining or parallel processing techniques. This paper proposes new architectures for quantization algorithms, which can be easily pipelined. These approaches are suitable for real time high-speed implementation of quantizer loop operations. The power consumption of the proposed architectures are less by the use of tristate buffers in the implementation.