Analysis of technology scaling impact on CMOS, CPL, and Domino logic styles using 0.8-, 0.6-, 0.35- and 0.25µm technologies

Author

Bisen, T.N. ; Palsodkar, P.M.

Author_Institution

Dept. of Electron. Eng., Yashwantrao Chavan Coll. of Eng., Nagpur, India

fYear

2009

fDate

4-6 June 2009

Firstpage

1

Lastpage

6

Abstract

This paper describes challenges of technology scaling on different CMOS logic styles, implemented using 0.8-, 0.6-, 0.35- and 0.25 mum CMOS technologies. Technology scaling impact is more adverse related with velocity saturation, mobility degradation, leakage current, VDD/ VTH ratio, hot carrier effect, drain induced barrier lowering effect. Three popular logic families namely: conventional CMOS, complementary pass logic and domino logic are implemented for different micron technologies and they are analyzed for optimum energy delay product, that analysis provides right choice of logic style for different applications.

Keywords

CMOS logic circuits; logic design; CMOS; CPL; VDD-VTH ratio; complementary pass logic; domino logic styles; drain-induced barrier lowering effect; hot carrier effect; leakage current; micron technology; mobility degradation; optimum energy delay product; scaling impact; size 0.25 mum; size 0.35 mum; size 0.6 mum; size 0.8 mum; velocity saturation; CMOS logic circuits; CMOS technology; Capacitance; Degradation; Educational institutions; Logic circuits; Logic devices; MOSFETs; Paper technology; Pulse inverters; CMOS; energy -delay; technology scaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Automation, Communication and Energy Conservation, 2009. INCACEC 2009. 2009 International Conference on

Conference_Location

Perundurai, Tamilnadu

Print_ISBN

978-1-4244-4789-3

Type

conf

Filename

5204492