A 0.6mW/Gbps, 6.4–8.0Gbps serial link receiver using local injection-locked ring oscillators in 90nm CMOS

Author

Hu, Kangmin ; Jiang, Tao ; Wang, Jingguang ; Mahony, Frank O. ; Chiang, Patrick Yin

Author_Institution

School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, 97331, USA

fYear

2009

fDate

16-18 June 2009

Firstpage

46

Lastpage

47

Abstract

This paper describes a quad-channel, 6.4–8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator for greater than one UI of phase deskew. Measured results show a 6.4–7.2Gbps data rate with BER ≪ 10⁻¹⁵ across 10cm of FR4 backplane, and 8.0Gpbs data rate with direct input. Designed in a 1.2V, 90nm CMOS process, the area of each receiver is 0.0174mm², with a measured power efficiency of 0.6mW/Gbps.

Keywords

Area measurement; Backplanes; Bit error rate; CMOS process; Clocks; Demultiplexing; Equalizers; Power measurement; Ring oscillators; Testing; Serial link; injection-locked oscillator; receiver;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2009 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

978-1-4244-3307-0

Electronic_ISBN

978-4-86348-001-8

Type

conf

Filename

5205297