Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme

A transceiver chip with per-pin de-skew and read latency detection scheme utilizing on-chip TDR was implemented in 60nm DRAM process for the interface with source synchronous clock system. Without multi-phase clock, each time skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate. Also, the jitter reduction of 50% was measured with swing-level controlled voltage-mode driver in the absence of destination termination at 1.6-Gb/s.