Title :
Technology portable, 0.04mm2, Ghz-rate ΔΣ modulators in 65nm and 45nm CMOS
Author :
van Veldhoven, Robert H.M. ; Nizza, Nicolo ; Breems, Lucien J.
Author_Institution :
NXP Semiconductor, High Tech Campus 37, office 2.017, Eindhoven, The Netherlands
Abstract :
An area reducing design methodology is used to design three 0.04mm2, 5th order, 1-bit, ΣΔ modulators. A 1.2V/65nm chip contains a feedback (FB) modulator sampled at 1GHz, and a 1.1V/45nm chip contains a FB and feed-forward (FF) modulator sampled at 1.5Ghz. Each modulator achieves an SNR of 60dB in 15MHz. Furthermore a method is presented, which perfectly compensates for excess phase in a ΣΔloop, without compromising loop stability and noise shaping.
Keywords :
Bandwidth; CMOS technology; Capacitors; Circuit noise; Costs; Design methodology; Feedback; Feedforward systems; Filters; Noise reduction;
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
