• DocumentCode
    497962
  • Title

    A 79dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC

  • Author

    Rajaee, O. ; Musah, T. ; Takeuchi, S. ; Aniya, M. ; Hamashita, K. ; Hanumolu, P. ; Moon, U.

  • Author_Institution
    School of EECS, Oregon State University, Corvallis, USA
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    74
  • Lastpage
    75
  • Abstract
    A new delta-sigma modulator architecture is presented. The proposed implementation employs a pipeline ADC as the quantizer of a single-loop delta-sigma modulator and makes use of inherent delays of pipeline ADC stages to enhance overall noise shaping properties. With a 5MHz bandwidth and 80MHz clock, the measured dynamic range and SNDR of this prototype IC are 79dB and 75.4dB. The prototype chip is implemented in a 0.18µm CMOS process.
  • Keywords
    Bandwidth; CMOS process; Clocks; Delay; Delta modulation; Dynamic range; Noise shaping; Pipelines; Prototypes; Semiconductor device measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205309
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497962