• DocumentCode
    497972
  • Title

    A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system

  • Author

    Wong, Cheng-Chi ; Lee, Yung-Yu ; Chang, Hsie-Chia

  • Author_Institution
    Department of Electronics Engineering, National Chiao Tung University, Taiwan, R.O.C
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    288
  • Lastpage
    289
  • Abstract
    This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a threestage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm2 chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
  • Keywords
    Code standards; Communication standards; Communication systems; Data communication; Hazards; Iterative decoding; Multiplexing; Parallel architectures; Parallel processing; Turbo codes; 3GPP LTE; QPP interleaver; turbo decoder;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205324
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497972