• DocumentCode
    497973
  • Title

    A 58-µW single-chip sensor node processor using synchronous MAC protocol

  • Author

    Takeuchi, Takashi ; Izumi, Shintaro ; Matsuda, Takashi ; Lee, Hyeokjong ; Otake, Yu ; Konishi, Toshihiro ; Tsuruda, Koh ; Sakai, Yasuharu ; Fujiwara, Hidehiro ; Ohta, Chikara ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko

  • Author_Institution
    Kobe University, 1-1 Rokkodai-Cho, Nada-Ku, 657-8501 Japan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    290
  • Lastpage
    291
  • Abstract
    We propose a single-chip ultralow-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3 × 3 mm2 in a 180-nm CMOS process, including 1.38 M transistors. The power is 58.0 µW under a network environment.
  • Keywords
    Costs; Energy management; Large scale integration; Media Access Protocol; Power amplifiers; Ring oscillators; Sensor systems; Testing; Transceivers; Wireless sensor networks; Wireless sensor network; low power; single-chip sensor node; synchronous MAC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205325
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497973