Title :
A 12b 11MS/s successive approximation ADC with two comparators in 0.13μm CMOS
Author :
Kang, Joshua J. ; Flynn, Michael P.
Author_Institution :
EECS, University of Michigan 1301 Beal Avenue, Ann Arbor, 48109 USA
Abstract :
A two-comparator architecture, incorporating deliberate comparator offset and pre-amplifier power management, reduces comparator meta-stability and comparator power consumption in a 12b 11MS/s SAR ADC. A prototype, fabricated in 0.13μm CMOS achieves an FOM, SNDR, SFDR and error rate of 311fJ/conversion step, 62.4dB and 72.8dB and ≪1.9×10−12, respectively, at 11MS/s.
Keywords :
CMOS technology; Delay; Energy consumption; Energy management; Logic; Metastasis; Prototypes; Redundancy; Semiconductor device measurement; Voltage; SAR ADC; two-comparator architecture;
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
