DocumentCode :
497994
Title :
3D system integration of processor and multi-stacked SRAMs by using inductive-coupling links
Author :
Osada, Kenichi ; Saen, Makoto ; Okuma, Yasuyuki ; Niitsu, Kiichi ; Shimazaki, Yasuhisa ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Kasuga, Kazutaka ; Nonomura, Itaru ; Irie, Naohiko ; Hattori, Toshihiro ; Hasegawa, Atsushi ; Kuroda, Tadahiro
Author_Institution :
Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
256
Lastpage :
257
Abstract :
This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an “open-skipped-inductor scheme” is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.
Keywords :
Bonding; Circuits; Degradation; Energy consumption; Inductors; SRAM chips; Signal processing; Timing; Transmitters; Wire; 3D system integration; inductive coupling link; memory; processor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
Type :
conf
Filename :
5205351
Link To Document :
بازگشت