Title :
A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias
Author :
Chun, Ki Chul ; Jain, Pulkit ; Lee, Jung Hwa ; Kim, Chris H.
Author_Institution :
Dept. of ECE, University of Minnesota, 200 Union Street SE, Minneapolis, 55455, USA
Abstract :
Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.
Keywords :
Boosting; CMOS logic circuits; CMOS process; Circuit testing; Logic testing; Random access memory; Semiconductor device measurement; Timing; Transistors; Voltage;
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
