Guess, solder, measure, repeat - How do I get my mixed-signal chip right?

Author

Ying, Geoffrey ; Kuehlmann, Andreas ; Kundert, Ken ; Gielen, George ; Grimme, Eric ; O´Leary, Martin ; Tare, Sandeep ; Wong, Warren

Author_Institution

Synopsys Inc., Mountain View, CA, USA

fYear

2009

fDate

26-31 July 2009

Firstpage

520

Lastpage

521

Abstract

Over the past 20 years, EDA has developed a solid digital implementation methodology that combines some restrictions on the design style with a set of comprehensive tools leading to predictable design flows. The recent increased use of analog components in complex SOC designs triggered a set of verification challenges ranging from simple connectivity problems to complex interferences between analog and digital data blocks. This panel discusses the state of the affairs in analog-mixed signal verification and draws a picture of future directions in terms of new approaches and tools.

Keywords

electronic design automation; logic design; logic testing; system-on-chip; SOC design; analog data block; analog-mixed signal verification; digital data block; electronic design automation; Analog circuits; Circuit simulation; Electronic design automation and methodology; Hardware design languages; Instruments; Integrated circuit modeling; Knowledge engineering; Permission; SPICE; Semiconductor device measurement; Analog Behavioral Modeling; Functional Verification; Low Power Verification; Mixed-signal Verification; Performance Verification; SPICE; VHDL; Verilog; Verilog-AMS;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

978-1-6055-8497-3

Type

conf

Filename

5227052