Optimum LDPC decoder: A memory architecture problem

This paper addresses a frequently overlooked problem: designing a memory architecture for an LDPC decoder. We analyze the requirements to support the codes defined in the IEEE 802.11n and 802.16 e standards. We show a design methodology for a flexible memory subsystem that reconciles design cost, energy consumption and required latency on a multistandard platform. We show results after exploring the design space on a CMOS technology of 65 nm and analyze various use cases from the standardized codes. Comparisons among representative work reveal the benefits of our exploration.