Title :
CMOS scaling beyond 32nm: Challenges and opportunities
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
This paper explores the challenges and opportunities facing CMOS process generations past the 32 nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations.
Keywords :
CMOS integrated circuits; CMOS; NMOS; PMOS; high-k metal-gate; multiple-gate devices; planar devices; CMOS process; CMOS technology; Capacitance; Capacitive sensors; Degradation; Doping; Electrostatic discharge; History; MOS devices; Stress; CMOS; high-k; metal-gate; orientation; strain;
Conference_Titel :
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-6055-8497-3
