DocumentCode :
500890
Title :
Soft connections: Addressing the hardware-design modularity problem
Author :
Pellauer, Michael ; Adler, Michael ; Chiou, Derek ; Emer, Joel
Author_Institution :
Comput. Sci. & A.I. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear :
2009
fDate :
26-31 July 2009
Firstpage :
276
Lastpage :
281
Abstract :
Hardware-design languages typically impose a rigid communication hierarchy that follows module instantiation. This leads to an undesirable side-effect where changes to a child´s interface result in changes to the parents. Soft connections address this problem by allowing the user to specify connection endpoints that are automatically connected at compilation time, rather than by the user.
Keywords :
field programmable gate arrays; hardware description languages; hardware-design languages; hardware-design modularity problem; module instantiation; soft connections; Computer science; Debugging; Field programmable gate arrays; Hardware design languages; Permission; Prefetching; Productivity; Software standards; Software tools; Wires; High-Level Communication Description;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
978-1-6055-8497-3
Type :
conf
Filename :
5227147
Link To Document :
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