Title :
Polynomial datapath optimization using partitioning and compensation heuristics
Author :
Sarbishei, O. ; Alizadeh, B. ; Fujita, M.
Author_Institution :
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
Abstract :
Datapath designs that perform polynomial computations over Z2 n are used in many applications such as computer graphics and digital signal processing domains. As the market of such applications continues to grow, improvements in high-level synthesis and optimization techniques for multivariate polynomials have become really challenging. This paper presents an efficient algorithm for optimizing the implementation of a multivariate polynomial over Z2 n in terms of the number of multipliers and adders. This approach makes use of promising heuristics to extract more complex common sub-expressions from the polynomial compared to the conventional methods. The proposed algorithm also utilizes a canonical decision diagram, Horner-expansion diagram (HED) [1] to reduce the polynomial´s degree over Z2 n. Experimental results have shown an average saving of 27% and 10% in terms of the number of logic gates and critical path delay respectively compared to existing high-level synthesis tools as well as state of the art algebraic approaches.
Keywords :
polynomials; Horner-expansion diagram; compensation heuristics; computer graphics; digital signal processing; multivariate polynomials; polynomial datapath optimization; Application software; Computer graphics; Delay; Digital signal processing; High level synthesis; Logic functions; Logic gates; Polynomials; Signal design; Signal processing algorithms; High-Level Synthesis; Modular HED; Polynomial Datapath;
Conference_Titel :
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-6055-8497-3