Title :
A stochastic jitter model for analyzing digital timing-recovery circuits
Author :
Burnham, James R. ; Yang, Chih-Kong Ken ; Hindi, Haitham
Author_Institution :
High-Q Design, Los Altos, CA, USA
Abstract :
This paper describes a stochastic jitter model for analyzing the performance and bit error rate (BER) of digital timing recovery circuits. The model uses parallel interconnected Markov chains to simulate the behavior of the system in response to both random and deterministic jitter. Unlike conventional Markov-chain models that require the system to be stationary, the parallel-chain model approximates deterministic changes in conditions with transitions between sub-chains. To verify the accuracy of the model, an analysis was performed on a digital delay-locked loop, and the results compared to measured data. The resulting transition probabilities and BER predicted by the proposed model are more than three orders of magnitude more accurate than those predicted by a conventional Markov-chain model.
Keywords :
Markov processes; delay lock loops; deterministic algorithms; digital circuits; synchronisation; timing jitter; bit error rate; deterministic jitter; digital delay locked loop; digital timing recovery circuits; parallel chain model; parallel interconnected Markov chains; random jitter; stochastic jitter model; Bit error rate; Circuit analysis; Circuit simulation; Delay; Integrated circuit interconnections; Performance analysis; Performance evaluation; Predictive models; Stochastic processes; Timing jitter; Jitter; Markov chain; bit-error-rate (BER); delay-locked loop (DLL); mean-time-between-failures (MTBF); stochastic model; timing margins; timing recovery circuits;
Conference_Titel :
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-6055-8497-3
