DocumentCode
500935
Title
Creating an affordable 22nm node using design-lithography co-optimization
Author
Strowjas, A.J. ; Jhaveri, T. ; Rovner, V. ; Pileggi, L.
Author_Institution
PDF Solutions Inc., San Jose, CA, USA
fYear
2009
fDate
26-31 July 2009
Firstpage
95
Lastpage
96
Abstract
Achieving the required time-to-market with economically acceptable yield levels and maintaining them in volume production has become a daunting task for the advanced technology nodes. These difficulties are primarily attributable to the increase in process variability that is incurred while aggressively scaling technology nodes which are based on the same fundamental device architectures and process solutions. The introduction of a metal gate/high-K (MGHK) stack at the 32/28 nm technology node will help in addressing the random variations due to random dopant fluctuations (RDF), but its benefit will be exhausted after a single process generation. As a result, for the 22/20 nm technology nodes, the only hope to limit RDF will be to adopt novel device architecture, such as FinFET and ultra thin body or fully depleted SOI, that would reduce the dopant concentration in the channel. Moreover, the inability to scale the wavelength of the light source used for lithography has led to a rapid increase of process and design costs. In particular, the lack of progress in extreme ultraviolet lithography (EUVL) will result in the need to define 22 nm technology node using expensive double patterning technologies (DPT) for critical layers. As a result, complex DFM flows have been proposed as an attempt to model various printability and layout dependent effects; however, the increase in design flow complexities, lack of accuracy, and the tremendous expense of maintaining updated models required for these methods has marred their adoption.We will show how template-based design methodology can enable future technology nodes that can utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choices of regular design fabrics and their implications on design metrics, such as power, area, and performance, resulting yields, and overall cost; show that the selection of circuit topologies can be mapped efficiently to the choice of reg- ular design fabric; and compare lithography solutions such as DPT, direct write multi-e-beam (MEBM), and interference lithography (IL) for the 22 nm technology node and beyond.
Keywords
high-k dielectric thin films; integrated circuit design; ultraviolet lithography; FinFET; SOI; advanced technology node; aggressive scaling technology node; design-lithography cooptimization; double patterning technologies; extreme ultraviolet lithography; interference lithography; metal gate-high-K stack; multie-beam lithography; random dopant fluctuation; size 20 nm; size 22 nm; size 28 nm; size 32 nm; template-based design methodology; Costs; Fabrics; Fluctuations; High K dielectric materials; High-K gate dielectrics; Lithography; Production; Resource description framework; Time to market; Ultraviolet sources; DFM; design technology co-optimization; regular fabric; templates;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-6055-8497-3
Type
conf
Filename
5227193
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