Title :
Jitter robust DRAM modeling
Author_Institution :
Qimonda AG, Munich, Germany
Abstract :
This paper presents jitter robust DRAM modeling. Jitter analysis of mixed mode PLL-DLL in DRAM environment has been carried out. According to the jitter type, this model can be used as pure PLL or pure DLL or a mixed PLL-DLL. It is observed that mixed mode PLL-DLL architecture can combine the advantage from both PLL and DLL to reduce jitter in DRAM which is very important to cover both consumer and commodity DRAM applications.
Keywords :
DRAM chips; digital phase locked loops; delay-locked loops; jitter analysis; jitter robust DRAM modeling; mixed mode PLL-DLL architecture; phase-locked loops; Circuit noise; Clocks; Consumer electronics; Delay; Jitter; Phase frequency detector; Phase locked loops; Random access memory; Robustness; Streaming media; DLL; DRAM; DRAM jitter; PLL; jitter transfer function; mixed PLL-DLL;
Conference_Titel :
Nonlinear Dynamics and Synchronization, 2009. INDS '09. 2nd International Workshop on
Conference_Location :
Klagenfurt
Print_ISBN :
978-1-4244-3844-0
DOI :
10.1109/INDS.2009.5227993
