Compensating for the keeper current of CMOS domino logic using a well designed NMOS transistor

Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. However, this type of logic has the drawback of low noise immunity especially when compared to complementary CMOS logic. This is due to the leakage current and charge sharing. So, a PMOS keeper must be used in order to compensate for this leakage. However, the use of a keeper in the conventional domino circuit degrades the speed of the circuit or results in an erroneous output due to the contention current. In this paper, a novel technique that acts to speed up the operation of domino logic and to improve its noise immunity using a weak keeper is proposed. In this technique, a well designed NMOS transistor will be connected to the dynamic node in order to draw the contention current during the evaluation phase. The term ldquowell designedrdquo will be illustrated through the paper. A modification to the proposed technique will also be presented in which the precharge device need not be increased in size. Simulation will be carried out for the 0.13 mum technology with V_DD=1.2 V for the case of AND gate with two inputs. Simulation results show that the speed improves by a factor of approximately 33% and the noise margin increases from only 100 mV to 600 mV in case the dynamic node is to be at logic ldquo0rdquo for the same transistor aspect ratios at the cost of adding only one NMOS transistor and increasing the size of the precharge device, or instead connecting two serially connected NMOS transistors to the dynamic node and keeping the size of the precharge device the same.