DocumentCode
501495
Title
Total-dose worst-case test vectors for leakage current failure induced in combinational circuits of cell-based ASICs
Author
Abou-Auf, Ahmed A.
Author_Institution
Electron. Eng. Dept., American Univ. in Cairo, Cairo, Egypt
fYear
2009
fDate
17-19 March 2009
Firstpage
1
Lastpage
7
Abstract
We developed a methodology for identifying worst-case test vectors for leakage current failure induced in combinational circuits of cell-based ASICs induced by total-dose. This methodology is independent on the design tools and the process technology.
Keywords
application specific integrated circuits; combinational circuits; leakage currents; cell-based ASIC; combinational circuits; design tools; leakage current failure; total-dose worst-case test vectors; Application specific integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Electronic equipment testing; Hardware design languages; Leakage current; Logic gates; MOSFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Science Conference, 2009. NRSC 2009. National
Conference_Location
New Cairo
ISSN
1110-6980
Print_ISBN
978-1-4244-4214-0
Type
conf
Filename
5233951
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