DocumentCode
501894
Title
Evaluation of diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13 µm CMOS logic technology
Author
Gauthier, Robert ; Stadler, Wolfgang ; Esmark, Kai ; Riess, Philipp ; Salman, Akram ; Muhammad, Mujahid ; Putnam, Chris
Author_Institution
Semicond. R&D Center, IBM Microelectron., Essex Junction, VT, USA
fYear
2001
fDate
11-13 Sept. 2001
Firstpage
203
Lastpage
213
Abstract
In a 0.13 mum CMOS technology, ESD protection solutions based on NFETs and diodes are compared and their applicability for several groups of digital I/Os are discussed. In order to enable the use of these strategies, there are process requirements which need to be considered during the technology definition.
Keywords
MOSFET; electrostatic discharge; semiconductor device breakdown; semiconductor device reliability; CMOS logic technology; Lnpn-based ESD protection strategy; MOSFET-based protection; NFET evaluation; NMOS-based ESD protection; size 0.13 mum; triple gate oxide thickness; Biological system modeling; CMOS logic circuits; CMOS technology; Electrostatic discharge; MOS devices; Microelectronics; Protection; Research and development; Robustness; Semiconductor diodes;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2001. EOS/ESD '01.
Conference_Location
Portland, OR
Print_ISBN
978-1-5853-7039-9
Electronic_ISBN
978-1-5853-7039-9
Type
conf
Filename
5254966
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