DocumentCode :
501918
Title :
ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device
Author :
Ker, Ming-Dou ; Chuang, Chien-Hui ; Jiang, Hsin-Chin
Author_Institution :
Integrated Circuits&Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
fYear :
2001
fDate :
11-13 Sept. 2001
Firstpage :
32
Lastpage :
43
Abstract :
A new ESD protection circuit, by using the stacked-NMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS IC´s. Without using the thick gate oxide, the experimental results in a 0.35-mum CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original ~2 kV to become > 8 kV by using this new proposed ESD protection circuit.
Keywords :
CMOS integrated circuits; MOSFET; clamps; electrostatic discharge; thyristors; ESD clamp device; ESD protection design; human-body-model; mixed-voltage I-O buffer; silicon controlled rectifier; size 0.35 mum; stacked-NMOS triggered SCR device; CMOS process; CMOS technology; Clamps; Electrostatic discharge; Integrated circuit technology; MOS devices; Power supplies; Protection; Thyristors; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2001. EOS/ESD '01.
Conference_Location :
Portland, OR
Print_ISBN :
978-1-5853-7039-9
Electronic_ISBN :
978-1-5853-7039-9
Type :
conf
Filename :
5254991
Link To Document :
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