Title :
An active ESD protection technique for the power domain boundary in a deep submicron IC
Author :
Kitagawa, N. ; Ishii, Hiroyuki ; Watanabe, J. ; Shiochi, M.
Author_Institution :
Toshiba Corp. Semicond. Co., Kawasaki, Japan
Abstract :
A novel ESD protection technique which prevents failure of boundary circuits in an IC with separated power pins from ESD stresses is proposed. In the proposed technique, the boundary circuits which are composed of drivers or receivers are controlled by an ESD detector to reduce stresses on the circuits during ESD events. Measurement results and physical analysis show that this technique improves the equivalent HBM level from 1.9 kV to 2.7 kV in test chips fabricated in a 90 nm CMOS process.
Keywords :
CMOS integrated circuits; electrostatic discharge; equivalent circuits; integrated circuit testing; system-on-chip; CMOS process; ESD detector; active ESD protection; boundary circuits; deep submicron IC; equivalent HBM level; power domain boundary; separated power pins; size 90 nm; system on chip; test chips; CMOS process; Circuit testing; Detectors; Driver circuits; Electrostatic discharge; Event detection; Pins; Protection; Semiconductor device measurement; Stress control;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-5853-7115-0
